Design Overview for rca16_top

PropertyValue
Project Name:d:\!projects\!skola\jpo\adders
Target Device:xc2s200e
Constraints File:rca16.ucf
Report Generated:Monday 03/20/06 at 22:15
Printable Summary (View as HTML)rca16_top_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs:474,7041% 
Logic Distribution:    
Number of occupied Slices:252,3521% 
Number of Slices containing only related logic:2525100% 
Number of Slices containing unrelated logic:0250% 
Total Number of 4 input LUTs:474,7041% 
Number of bonded IOBs:5314237% 
Number of GCLKs:1425% 
Number of GCLKIOBs:1425% 

Performance Summary

PropertyValue
Final Timing Score:22300
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints (total failing = 1)

Constraint(s)RequestedActualLogic Levels
* TS_clk = PERIOD TIMEGRP "clk" 15 ns HIGH50% 15.000ns21.259ns16

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentMonday 03/20/06 at 22:15
Translation ReportCurrentMonday 03/20/06 at 22:15
Map ReportCurrentMonday 03/20/06 at 22:15
Pad ReportCurrentMonday 03/20/06 at 22:15
Place and Route ReportCurrentMonday 03/20/06 at 22:15
Post Place and Route Static Timing ReportCurrentMonday 03/20/06 at 22:15