Design Overview for cla16vhd_top

PropertyValue
Project Name:d:\!projects\!skola\jpo\adders
Target Device:xc2s200e
Constraints File:cla16vhd.ucf
Report Generated:Monday 03/20/06 at 22:13
Printable Summary (View as HTML)cla16vhd_top_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs:714,7041% 
Logic Distribution:    
Number of occupied Slices:402,3521% 
Number of Slices containing only related logic:4040100% 
Number of Slices containing unrelated logic:0400% 
Total Number of 4 input LUTs:714,7041% 
Number of bonded IOBs:5314237% 
Number of GCLKs:1425% 
Number of GCLKIOBs:1425% 

Performance Summary

PropertyValue
Final Timing Score:0
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
All Constraints Met   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentMonday 03/20/06 at 22:12
Translation ReportCurrentMonday 03/20/06 at 22:13
Map ReportCurrentMonday 03/20/06 at 22:13
Pad ReportCurrentMonday 03/20/06 at 22:13
Place and Route ReportCurrentMonday 03/20/06 at 22:13
Post Place and Route Static Timing ReportCurrentMonday 03/20/06 at 22:13